Applying ROBDDs for Logical Circuit Delay Testing

Статья в журнале

Increasing frequency of functioning and decreasing transistor sizes in high performance logical circuits may result in illegal capacities, inductivities, resistances, and so on that generate decreasing estimated circuit frequency. These defects cannot be detected by physical methods. The main way of solving the problem is based on delay testing of logical circuits within the path delay fault (PDF) model. In this paper, facilities of enhancing PDF test sequence quality based on application of Reduced Ordered Binary Decision Diagrams (ROBDDs) that compactly represent all test pairs of neighbor test patterns for the circuit path are studied. Test patterns (Boolean vectors) are neighbor if they differ by only one component. It is established that using of these ROBDDs cut the lengths of test sequences by more than 1/3 in comparison with traditional scan test sequences simultaneously enhancing test sequence quality. In particular, we derive test sequences for robust testable PDFs of sequential circuits decreasing their power consumption and peak power values.

Журнал:

Russian Physics Journal
Springer US (New York City)

Библиографическая запись: Applying ROBDDs for Logical Circuit Delay Testing / A. Yu. Matrosova [et. al.] // Russian Physics Journal. - Vol. 62. Iss. 5. - P. 827-834. - DOI: 10.1007/s11182-019-01784-y

Ключевые слова:

COMBINATIONAL AND SEQUENTIAL CIRCUITS EQUIVALENT NORMAL FORM ROBUST TESTABLE PDFS

Индексируется в:

Авторы: Матросова А. Ю., Андреева В. В., Тычинский В. З., Гошин Г. Г.

Год издания: 2019

Страницы: 827 - 834

Язык: Английский

DOI: 10.1007/s11182-019-01784-y